MC9S12XF512MLM Datasheet, PDF (78/1306 Pages) Freescale Semiconductor, Inc – S12X Microcontrollers

Chapter 1 MC9S12XF-Family Reference Manual
1.8 ATD External Trigger Input Connection
The ATD module includes four external trigger inputs ETRIG0, ETRIG1, ETRIG2, and ETRIG3. The
external trigger allows the user to synchronize ATD conversion to external trigger events. Table 1-17
shows the connection of the external trigger inputs.
Table 1-17. ATD0 External Trigger Sources
External Trigger
Input
Connectivity
ETRIG0
Start of PWM Cycle Channel A⁽¹⁾
ETRIG1
EPIT - Combined Trigger⁽²⁾
ETRIG2
EPIT - Hardware Trigger 0⁽³⁾
ETRIG3
1. Indicates start of new PWM cycle.
EPIT - Hardware Trigger 1⁽⁴⁾
2. Selectable hardware trigger. One of eight EPIT channels can be selected. The trigger interval
is started via a PMF output.
3. Interrupt timer hardware trigger channel 0
4. Interrupt timer hardware trigger channel 1
Consult the EPIT block description for more information about hardware trigger generation.
Consult the ATD block description for information about the analog-to-digital converter module. ATD
block description refererences to freeze mode are equivalent to active BDM mode.
1.9 MPU Configuration
The MPU can handle 3 bus masters (CPU + XGATE + FlexRay). The MPU covers the system ram address
space. See MPU documentation for more details.
Table 1-18. MPU Configuration
Parameter
Parameter
Value
Number of Descriptors
4
Descripter Granularity⁽¹⁾
8
1. Number of least significant address bits to
treat as constant.
NOTE
• The FlexRay module is Master 3 (MSTR3)
• CPU user state is not supported
on this device.
MC9S12XF - Family Reference Manual, Rev.1.20
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Freescale Semiconductor