MC9S12XF512MLM Datasheet, PDF (450/1306 Pages) Freescale Semiconductor, Inc – S12X Microcontrollers

Chapter 12 Clock Generation Module using IPLL (CGMIPLL) Block Description
Module Base + 0x0000
7
6
5
4
3
2
1
0
R
VCOFRQ[1:0]
W
SYNDIV[5:0]
Reset
0
0
0
0
0
0
0
0
Figure 12-3. CGMIPLL Synthesizer Register (CGMSYNR)
Read: Anytime
Write: Anytime
Writing the CGMSYNR register clears the LOCK status bit.
f _VCO = 2 × f _OSC × ⁽-₍--^SR---^Y-_E---^N-_F----_DD----_I-^I--_VV------₊₊----₁-¹---₎₎-
f _CGMIPLL = f _{VCO (IF DIV2=0)}
f _CGMIPLL = ^f---^V----₂-^C----^O--- (IF DIV2=1)
NOTE
f_VCO must be within the specified VCO frequency lock range. f_CGMIPLL
must not exceed the specified maximum.
The VCOFRQ[1:0] bit are used to configure the VCO gain for optimal stability and lock time. For correct
IPLL operation the VCOFRQ[1:0] bits have to be selected according to the actual target VCOCLK
frequency as shown in Table 12-1. Setting the VCOFRQ[1:0] bits wrong can result in a non functional
IPLL (no locking and/or insufficient stability).
Table 12-1. VCO Clock Frequency Selection
VCOCLK Frequency Ranges
32MHz <= f_VCO<= 48MHz
48MHz < f_VCO<= 80MHz
Reserved
80MHz < f_VCO <= 120MHz
VCOFRQ[1:0]
00
01
10
11
12.3.2.2 CGMIPLL Reference Divider Register (CGMREFDV)
The REFDV register provides a finer granularity for the IPLL multiplier steps.
MC9S12XF - Family Reference Manual, Rev.1.20
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Freescale Semiconductor