MC9S12XF512MLM Datasheet, PDF (546/1306 Pages) Freescale Semiconductor, Inc – S12X Microcontrollers

Chapter 13 FlexRay Communication Controller (FLEXRAY)
13.6.3.6 Receive Shadow Buffer Configuration Data
Before frame reception into the individual message buffers can be performed, the receive shadow buffers
must be configured. The configuration data are provided by the Receive Shadow Buffer Index Register
(RSBIR). For each receive shadow buffer, the application provides the message buffer header index. When
the protocol is in the POC:normal active or POC:normal passive state, the receive shadow buffers are
under full FlexRay block control.
13.6.3.7 Receive FIFO Control and Configuration Data
This section describes the configuration and control data for the two receive FIFOs.
13.6.3.7.1 Receive FIFO Configuration Data
The FlexRay block provides two completely independent receive FIFOs, one per channel. Each FIFO has
its own set of configuration data. The configuration data are located in the following registers:
• Receive FIFO Start Index Register (RFSIR)
• Receive FIFO Depth and Size Register (RFDSR)
• Receive FIFO Message ID Acceptance Filter Value Register (RFMIDAFVR)
• Receive FIFO Message ID Acceptance Filter Mask Register (RFMIAFMR)
• Receive FIFO Frame ID Rejection Filter Value Register (RFFIDRFVR)
• Receive FIFO Frame ID Rejection Filter Mask Register (RFFIDRFMR)
• Receive FIFO Range Filter Configuration Register (RFRFCFR)
13.6.3.7.2 Receive FIFO Control Data
The application can access the receive FIFO at any time using the values provided in the Receive FIFO A
Read Index Register (RFARIR) and Receive FIFO B Read Index Register (RFBRIR). To update the
Receive FIFO A Read Index Register (RFARIR), the application must write 1 to the FIFO A Not Empty
Interrupt Flag FNEAIF in the Global Interrupt Flag and Enable Register (GIFER). To update the Receive
FIFO B Read Index Register (RFBRIR) the application must write 1 to the FIFO B Not Empty Interrupt
Flag FNEBIF in the Global Interrupt Flag and Enable Register (GIFER). As long as the FIFO is not empty,
each update increments the related read index. If the read index has reached the last FIFO entry, it wraps
back to the FIFO start index.
13.6.4 FlexRay Memory Layout
The FlexRay block supports a wide range of possible layouts for the FRM. Figure 13-104 shows an
example layout. The following set of rules applies to the layout of the FRM:
• The FRM is a contiguous region.
• The FRM size is maximum 64 Kbytes.
• The FRM starts at a 16 byte boundary.
The FRM contains three areas: the message buffer header area, the message buffer data area, and the sync
frame table area. The areas are described in this section.
MC9S12XF - Family Reference Manual, Rev.1.19
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