MC9S12XF512MLM Datasheet, PDF (111/1306 Pages) Freescale Semiconductor, Inc – S12X Microcontrollers

Chapter 2 S12XE Clocks and Reset Generator (S12XECRG)
S12XECRG performs a quality check on the incoming clock signal. As soon as clock quality check
indicates a valid Oscillator Clock signal the reset sequence starts using the Oscillator clock. If after 50
check windows the clock quality check indicated a non-valid Oscillator Clock the reset sequence starts
using Self-Clock Mode.
Figure 2-22 and Figure 2-23 show the power-up sequence for cases when the RESET pin is tied to V_DD
and when the RESET pin is held low.
RESET
Clock Quality Check
(no Self-Clock Mode)
)(
Internal POR
Internal RESET
)(
128 SYSCLK
)(
64 SYSCLK
Figure 2-22. RESET Pin Tied to V_DD (by a Pull-up Resistor)
RESET
Clock Quality Check
(no Self Clock Mode)
)(
Internal POR
Internal RESET
)(
128 SYSCLK
)(
64 SYSCLK
Figure 2-23. RESET Pin Held Low Externally
2.6 Interrupts
The interrupts/reset vectors requested by the S12XECRG are listed in Table 2-18. Refer to MCU
specification for related vector addresses and priorities.
Table 2-18. S12XECRG Interrupt Vectors
Interrupt Source
Real time interrupt
LOCK interrupt
SCM interrupt
CCR
Mask
I bit
I bit
I bit
Local Enable
CRGINT (RTIE)
CRGINT (LOCKIE)
CRGINT (SCMIE)
MC9S12XF - Family Reference Manual, Rev.1.20
Freescale Semiconductor
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