IMX35 Datasheet, PDF (74/148 Pages) Power-One – 35 Watt DC-DC Converters

Table 52. Synchronous Display Interface Timing Parameters—Pixel Level (continued)
ID
IP9
IP10
IP11
IP12
IP13
Parameter
Horizontal blank interval 1
Horizontal blank interval 2
HSYNC delay
Screen height
VSYNC width
IP14
Vertical blank interval 1
IP15
Vertical blank interval 2
1 _{Display interface clock period immediate value}
Symbol
Thbi1
Thbi2
Thsd
Tsh
Tvsw
Tvbi1
Tvbi2
Value
BGXP × Tdpcp
(SCREEN_WIDTH – BGXP – FW) × Tdpcp
H_SYNC_DELAY × Tdpcp
(SCREEN_HEIGHT + 1) × Tsw
if V_SYNC_WIDTH_L = 0 than
(V_SYNC_WIDTH + 1) × Tdpcp
else
(V_SYNC_WIDTH + 1) × Tsw
BGYP × Tsw
(SCREEN_HEIGHT – BGYP – FH) × Tsw
Units
ns
ns
ns
ns
ns
ns
ns
Display interface clock period average value.
Tdicp = THSP_CLK ⋅ ^{D-----I--S-H--P--S--3--P_---_I--F-C---_-L--C--K--L--_--K-P---_E---P-R--E--I--RO----_D---W-----R---}
Figure 51 depicts the synchronous display interface timing for access level, and Table 53 lists the timing
parameters. The DISP3_IF_CLK_DOWN_WR and DISP3_IF_CLK_UP_WR parameters are set via the
DI_DISP3_TIME_CONF Register.
DISPB_D3_VSYNC
DISPB_D3_HSYNC
DISPB_D3_DRDY
other controls
DISPB_D3_CLK
IP20
IP16
IP17
IP19
IP18
DISPB_DATA
Figure 51. Synchronous Display Interface Timing Diagram—Access Level
i.MX35 Applications Processors for Automotive Products, Rev. 6
74
Freescale Semiconductor