IMX35 Datasheet, PDF (65/148 Pages) Power-One – 35 Watt DC-DC Converters

4.9.8.3 MII Transmit Signal Timing
The transmitter timing signals consist of FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER, and
FEC_TX_CLK. The transmitter functions correctly up to a FEC_TX_CLK maximum frequency of
25 MHz + 1%. There is no minimum frequency requirement. Additionally, the processor clock frequency
must exceed twice the FEC_TX_CLK frequency. Table 46 lists MII transmit channel timings.
Table 46. MII Transmit Signal Timing
Num
Characteristic¹
Min.
Max.
Unit
M5 FEC_TX_CLK to FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER
invalid
M6 FEC_TX_CLK to FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER
valid
M7 FEC_TX_CLK pulse width high
M8 FEC_TX_CLK pulse width low
5
—
35%
35%
—
20
65%
65%
ns
ns
FEC_TX_CLK period
FEC_TX_CLK period
1 _{FEC_TX_EN, FEC_TX_CLK, and FEC_TXD0 have the same timing when in 10 Mbps 7-wire interface mode.}
Figure 41 shows the MII transmit signal timings listed in Table 46.
M7
FEC_TX_CLK (input)
FEC_TXD[3:0] (outputs)
FEC_TX_EN
FEC_TX_ER
M5
M8
M6
Figure 41. MII Transmit Signal Timing Diagram
4.9.8.4 MII Asynchronous Inputs Signal Timing
The MII asynchronous timing signals are FEC_CRS and FEC_COL. Table 47 lists MII asynchronous
inputs signal timing.
Table 47. MII Asynch Inputs Signal Timing
Num
M9¹
Characteristic
FEC_CRS to FEC_COL minimum pulse width
Min.
1.5
Max.
—
Unit
FEC_TX_CLK period
1 _{FEC_COL has the same timing in 10 Mbit 7-wire interface mode.}
i.MX35 Applications Processors for Automotive Products, Rev. 6
Freescale Semiconductor
65