IMX35 Datasheet, PDF (48/148 Pages) Power-One – 35 Watt DC-DC Converters

4.9.5.3 ESDCTL Electrical Specifications
Figure 27 through Figure 36 depict the timings pertaining to the ESDCTL module, which interfaces with
mobile DDR or SDR SDRAM. Table 33 through Table 42 list the timing parameters.
SDCLK
SDCLK
CS
SD1
SD2
SD4
SD3
SD5
SD4
RAS
CAS
SD5
SD4
SD4
WE
SD5
SD5
SD6
ADDR
ROW/BA
SD7
COL/BA
SD10
DQ
SD8
SD9
Data
SD4
DQM
Note: CKE is high during the read/write cycle.
SD5
Figure 27. SDRAM Read Cycle Timing Diagram
Table 33. DDR/SDR SDRAM Read Cycle Timing Parameters
ID
Parameter
SD1 SDRAM clock high-level width
SD2 SDRAM clock low-level width
SD3 SDRAM clock cycle time
SD4 CS, RAS, CAS, WE, DQM, CKE setup time
SD5 CS, RAS, CAS, WE, DQM, CKE hold time
SD6 Address setup time
Symbol
Min. Max.
Unit
tCH
3.4
4.1
ns
tCL
3.4
4.1
ns
tCK
7.0
—
ns
tCMS
2.0
—
ns
tCMH
1.8
—
ns
tAS
2.0
—
ns
i.MX35 Applications Processors for Automotive Products, Rev. 6
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Freescale Semiconductor