K50P100M100SF2V2 Datasheet, PDF (63/79 Pages) Freescale Semiconductor, Inc – K50 Sub-Family

Num
DS9
DS10
DS11
DS12
DS13
DS14
DS15
DS16
Peripheral operating requirements and behaviors
Table 48. Slave mode DSPI timing (full voltage range) (continued)
Description
Frequency of operation
DSPI_SCK input cycle time
DSPI_SCK input high/low time
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
DSPI_SS active to DSPI_SOUT driven
DSPI_SS inactive to DSPI_SOUT not driven
Min.
—
8 x t_BUS
(t_SCK/2) - 4
—
0
3.2
7
—
—
Max.
6.25
—
(t_SCK/2) + 4
24
—
—
—
19
19
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
DSPI_SS
DSPI_SCK
(CPOL=0)
DSPI_SOUT
DSPI_SIN
DS10
DS15
DS13
First data
DS14
First data
DS12
Data
Data
DS9
DS11
Last data
DS16
Last data
Figure 23. DSPI classic SPI timing — slave mode
6.8.6 _I²_{C switching specifications}
See General switching specifications.
6.8.7 UART switching specifications
See General switching specifications.
K50 Sub-Family Data Sheet, Rev. 1, 6/2012.
Freescale Semiconductor, Inc.
Preliminary
63
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