K50P100M100SF2V2 Datasheet, PDF (22/79 Pages) Freescale Semiconductor, Inc – K50 Sub-Family

Peripheral operating requirements and behaviors
Board type
Single-layer (1s)
Symbol
R_θJMA
Four-layer (2s2p) R_θJMA
—
R_θJB
—
R_θJC
—
Ψ_JT
Description
100 LQFP
Thermal
37
resistance, junction
to ambient (200 ft./
min. air speed)
Thermal
29
resistance, junction
to ambient (200 ft./
min. air speed)
Thermal
20
resistance, junction
to board
Thermal
9
resistance, junction
to case
Thermal
2
characterization
parameter, junction
to package top
outside center
(natural
convection)
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
Notes
1
1
2
3
4
1.
Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method
Environmental Conditions—Forced Convection (Moving Air).
2.
Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental
Conditions—Junction-to-Board.
3.
Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate
temperature used for the case temperature. The value includes the thermal resistance of the interface material
between the top of the package and the cold plate.
4.
Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air).
6 Peripheral operating requirements and behaviors
6.1 Core modules
6.1.1 Debug trace timing specifications
Table 12. Debug trace operating behaviors
Symbol
T_cyc
T_wl
T_wh
T_r
Description
Clock period
Low pulse width
High pulse width
Clock and data rise time
Min.
Max.
Frequency dependent
2
—
2
—
—
3
Unit
MHz
ns
ns
ns
Table continues on the next page...
K50 Sub-Family Data Sheet, Rev. 1, 6/2012.
22
Preliminary
Freescale Semiconductor, Inc.
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