K50P100M100SF2V2 Datasheet, PDF (23/79 Pages) Freescale Semiconductor, Inc – K50 Sub-Family

Symbol
T_f
T_s
T_h
Peripheral operating requirements and behaviors
Table 12. Debug trace operating behaviors (continued)
Description
Clock and data fall time
Data setup
Data hold
Min.
Max.
Unit
—
3
ns
3
—
ns
2
—
ns
Figure 3. TRACE_CLKOUT specifications
TRACE_CLKOUT
TRACE_D[3:0]
Ts
Th
Ts
Th
Figure 4. Trace data specifications
6.1.2 JTAG electricals
Table 13. JTAG limited voltage range electricals
Symbol
J1
Description
Operating voltage
TCLK frequency of operation
• Boundary Scan
• JTAG and CJTAG
• Serial Wire Debug
Min.
2.7
0
0
0
Max.
3.6
10
25
50
J2
TCLK cycle period
J3
TCLK clock pulse width
• Boundary Scan
• JTAG and CJTAG
• Serial Wire Debug
1/J1
—
50
—
20
—
10
—
J4
TCLK rise and fall times
J5
Boundary scan input data setup time to TCLK rise
—
3
20
—
Table continues on the next page...
Freescale Semiconductor, Inc.
K50 Sub-Family Data Sheet, Rev. 1, 6/2012.
Preliminary
General Business Information
Unit
V
MHz
ns
ns
ns
ns
ns
ns
23