K50P100M100SF2V2 Datasheet, PDF (60/79 Pages) Freescale Semiconductor, Inc – K50 Sub-Family

Peripheral operating requirements and behaviors
Table 44. USB VREG electrical specifications
(continued)
Symbol Description
ESR
I_LIM
External output capacitor equivalent series
resistance
Short circuit current
Min.
1
—
Typ.¹
—
290
Max.
100
—
Unit
Notes
mΩ
mA
1. Typical values assume VREGIN = 5.0 V, Temp = 25 °C unless otherwise stated.
2. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to I_Load.
6.8.4 DSPI switching specifications (limited voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The tables
below provide DSPI timing characteristics for classic SPI timing modes. Refer to the
DSPI chapter of the Reference Manual for information on the modified transfer formats
used for communicating with slower peripheral devices.
Table 45. Master mode DSPI timing (limited voltage range)
Num
DS1
DS2
DS3
Description
Operating voltage
Frequency of operation
DSPI_SCK output cycle time
DSPI_SCK output high/low time
DSPI_PCSn valid to DSPI_SCK delay
DS4 DSPI_SCK to DSPI_PCSn invalid delay
DS5 DSPI_SCK to DSPI_SOUT valid
DS6 DSPI_SCK to DSPI_SOUT invalid
DS7 DSPI_SIN to DSPI_SCK input setup
DS8 DSPI_SCK to DSPI_SIN input hold
Min.
2.7
—
2 x t_BUS
(t_SCK/2) − 2
(t_BUS x 2) −
2
(t_BUS x 2) −
2
—
0
14
0
Max.
3.6
25
—
(t_SCK/2) + 2
—
—
8
—
—
—
Unit
V
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Notes
1
2
1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
K50 Sub-Family Data Sheet, Rev. 1, 6/2012.
60
Preliminary
Freescale Semiconductor, Inc.
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