K30P144M100SF2_1109 Datasheet, PDF (56/72 Pages) Freescale Semiconductor, Inc – K30 Sub-Family Data Sheet

Peripheral operating requirements and behaviors
Table 42. SDHC switching specifications
(continued)
Num
SD1
SD2
SD3
SD4
SD5
SD6
SD7
SD8
Symbol
fpp
fpp
fpp
f_OD
t_WL
t_WH
t_TLH
t_THL
t_OD
t_ISU
t_IH
Description
Clock frequency (low speed)
Min.
0
Max.
400
Clock frequency (SD\SDIO full speed)
0
25
Clock frequency (MMC full speed)
0
20
Clock frequency (identification mode)
0
400
Clock low time
7
—
Clock high time
7
—
Clock rise time
—
3
Clock fall time
—
3
SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SDHC output delay (output valid)
-5
6.5
SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SDHC input setup time
5
—
SDHC input hold time
0
—
Unit
kHz
MHz
MHz
kHz
ns
ns
ns
ns
ns
ns
ns
SDHC_CLK
Output SDHC_CMD
Output SDHC_DAT[3:0]
Input SDHC_CMD
Input SDHC_DAT[3:0]
SD3
SD2
SD1
SD6
SD7
SD8
Figure 23. SDHC timing
6.8.7 _I²_{S switching specifications}
This section provides the AC timings for the I²S in master (clocks driven) and slave
modes (clocks input). All timings are given for non-inverted serial clock polarity
(TCR[TSCKP] = 0, RCR[RSCKP] = 0) and a non-inverted frame sync (TCR[TFSI] = 0,
K30 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
56
Freescale Semiconductor, Inc.