56F8037_07 Datasheet, PDF (55/180 Pages) Freescale Semiconductor, Inc – 16-bit Digital Signal Controllers

Peripheral Memory-Mapped Registers
Register Acronym
SIM_CTRL
SIM_RSTAT
SIM_SWC0
SIM_SWC1
SIM_SWC2
SIM_SWC3
SIM_MSHID
SIM_LSHID
SIM_PWR
SIM_CLKOUT
SIM_PCR
SIM_PCE0
SIM_PCE1
SIM_SD0
SIM_SD1
SIM_IOSAHI
SIM_IOSALO
SIM_PROT
SIM_GPSA0
SIM_GPSA1
SIM_GPSB0
SIM_GPSB1
SIM_GPSCD
SIM_IPS0
SIM_IPS1
SIM_IPS2
Table 4-12 SIM Registers Address Map
(SIM_BASE = $00 F100)
Address Offset
Register Description
$0
Control Register
$1
Reset Status Register
$2
Software Control Register 0
$3
Software Control Register 1
$4
Software Control Register 2
$5
Software Control Register 3
$6
Most Significant Half JTAG ID
$7
Least Significant Half JTAG ID
$8
Power Control Register
Reserved
$A
Clock Out Select Register
$B
Peripheral Clock Rate Register
$C
Peripheral Clock Enable Register 0
$D
Peripheral Clock Enable Register 1
$E
Peripheral STOP Disable Register 0
$F
Peripheral STOP Disable Register 1
$10
I/O Short Address Location High Register
$11
I/O Short Address Location Low Register
$12
Protection Register
$13
GPIO Peripheral Select Register 0 for GPIOA
$14
GPIO Peripheral Select Register 1 for GPIOA
$15
GPIO Peripheral Select Register 0 for GPIOB
$16
GPIO Peripheral Select Register 1 for GPIOB
$17
GPIO Peripheral Select Register for GPIOC and GPIOD
$18
Internal Peripheral Source Select Register 0 for PWM
$19
Internal Peripheral Source Select Register 1 for DACs
$1A
Internal Peripheral Source Select Register 2 for TMRA
Reserved
Table 4-13 Computer Operating Properly Registers Address Map
(COP_BASE = $00 F120)
Register Acronym Address Offset
Register Description
COP_CTRL
COP_TOUT
COP_CNTR
$0
Control Register
$1
Time-Out Register
$2
Counter Register
56F8037 Data Sheet, Rev. 3
Freescale Semiconductor
55
Preliminary