56F8037_07 Datasheet, PDF (103/180 Pages) Freescale Semiconductor, Inc – 16-bit Digital Signal Controllers

Register Descriptions
6.3.11.3 Digital-to-Analog Converter 1 Clock Stop Disable (DAC1_SD)—Bit 13
• 0 = The clock is disabled during Stop mode
• 1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0
register
6.3.11.4 Digital-to-Analog Converter 0 Clock Stop Disable (DAC0_SD)—Bit 12
• 0 = The clock is disabled during Stop mode
• 1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0
register
6.3.11.5 Reserved—Bit 11
This bit field is reserved. It must be set to 0.
6.3.11.6 Analog-to-Digital Converter Clock Stop Disable (ADC_SD)—Bit 10
• 0 = The clock is disabled during Stop mode
• 1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0
register
6.3.11.7 Reserved—Bits 9–7
This bit field is reserved. Each bit must be set to 0.
6.3.11.8 Inter-Integrated Circuit Clock Stop Disable (I2C_SD)—Bit 6
• 0 = The clock is disabled during Stop mode
• 1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0
register
6.3.11.9 QSCI1 Clock Stop Disable (QSCI1_SD)—Bit 5
• 0 = The clock is disabled during Stop mode
• 1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0
register
6.3.11.10 QSCI0 Clock Stop Disable (QSCI0_SD)—Bit 4
• 0 = The clock is disabled during Stop mode
• 1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0
register
6.3.11.11 QSPI1 Clock Stop Disable (QSPI1_SD)—Bit 3
• 0 = The clock is disabled during Stop mode
• 1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0
register
56F8037 Data Sheet, Rev. 3
Freescale Semiconductor
103
Preliminary