56F8037_07 Datasheet, PDF (106/180 Pages) Freescale Semiconductor, Inc – 16-bit Digital Signal Controllers

6.3.13 I/O Short Address Location Register High (SIM_IOSAHI)
In I/O short address mode, the instruction specifies only 6 LSBs of the effective address; the upper 18 bits
are “hard coded” to a specific area of memory. This scheme allows efficient access to a 64-location area
in peripheral space with single word instruction. Short address location registers specify the upper 18 bits
of I/O address, which are “hard coded”. These registers allow access to peripherals using I/O short address
mode, regardless of the physical location of the peripheral, as shown in Figure 6-14.
“Hard Coded” Address Portion ^{Instruction Portion}
6 Bits from I/O Short Address Mode Instruction
16 Bits from SIM_IOSALO Register
2 bits from SIM_IOSAHI Register
Full 24-Bit for Short I/O Address
Figure 6-14 I/O Short Address Determination
With this register set, software can set the SIM_IOSAHI and SIM_IOSALO registers to point to its
peripheral registers and then use the I/O short addressing mode to access them.
Note: The default value of this register set points to the EOnCE registers.
Note:
The pipeline delay between setting this register set and using short I/O addressing with the new value
is five instruction cycles.
Base + $10 15 14 13 12 11 10 9
8
7
6
5
4
3
Read
0
0
0
0
0
0
0
0
0
0
0
0
0
Write
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
2
10
0
ISAL[23:22]
0
1
1
Figure 6-15 I/O Short Address Location High Register (SIM_IOSAHI)
6.3.13.1 Reserved—Bits 15—2
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.3.13.2 Input/Output Short Address Location (ISAL[23:22])—Bits 1–0
This field represents the upper two address bits of the “hard coded” I/O short address.
56F8037 Data Sheet, Rev. 3
106
Freescale Semiconductor
Preliminary