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MC56F8367 Datasheet, PDF (53/184 Pages) Freescale Semiconductor, Inc – 16-bit Digital Signal Controllers
Peripheral Memory Mapped Registers
Table 4-11 Quad Timer A Registers Address Map (Continued)
(TMRA_BASE = $00 F040)
Register Acronym Address Offset
Register Description
TMRA2_CMP1
TMRA2_CMP2
TMRA2_CAP
TMRA2_LOAD
TMRA2_HOLD
TMRA2_CNTR
TMRA2_CTRL
TMRA2_SCR
TMRA2_CMPLD1
TMRA2_CMPLD2
TMRA2_COMSCR
TMRA3_CMP1
TMRA3_CMP2
TMRA3_CAP
TMRA3_LOAD
TMRA3_HOLD
TMRA3_CNTR
TMRA3_CTRL
TMRA3_SCR
TMRA3_CMPLD1
TMRA3_CMPLD2
TMRA3_COMSCR
Reserved
$20
Compare Register 1
$21
Compare Register 2
$22
Capture Register
$23
Load Register
$24
Hold Register
$25
Counter Register
$26
Control Register
$27
Status and Control Register
$28
Comparator Load Register 1
$29
Comparator Load Register 2
$2A
Comparator Status and Control Register
Reserved
$30
Compare Register 1
$31
Compare Register 2
$32
Capture Register
$33
Load Register
$34
Hold Register
$35
Counter Register
$36
Control Register
$37
Status and Control Register
$38
Comparator Load Register 1
$39
Comparator Load Register 2
$3A
Comparator Status and Control Register
Table 4-12 Quad Timer B Registers Address Map
(TMRB_BASE = $00 F080)
Quad Timer B is NOT available in the 56F8167 device
Register Acronym Address Offset
Register Description
TMRB0_CMP1
TMRB0_CMP2
TMRB0_CAP
TMRB0_LOAD
TMRB0_HOLD
$0
Compare Register 1
$1
Compare Register 2
$2
Capture Register
$3
Load Register
$4
Hold Register
56F8367 Technical Data, Rev. 7.0
Freescale Semiconductor
53
Preliminary