MC56F8367 Datasheet, PDF (159/184 Pages) Freescale Semiconductor, Inc – 16-bit Digital Signal Controllers

Controller Area Network (CAN) Timing
10.14 Controller Area Network (CAN) Timing
Note: CAN is not available in the 56F8167 device.
Table 10-22 CAN Timing¹
Characteristic
Symbol
Min
Baud Rate
BR_CAN
—
Bus Wake Up detection
T _WAKEUP
5
1. Parameters listed are guaranteed by design
Max
1
—
Unit
Mbps
µs
See Figure
—
10-18
CAN_RX
CAN receive
data pin
(Input)
T _WAKEUP
Figure 10-18 Bus Wakeup Detection
10.15 JTAG Timing
Table 10-23 JTAG Timing
Characteristic
Symbol
Min
Max
TCK frequency of operation using EOnCE¹
f_OP
DC
TCK frequency of operation not using EOnCE¹
f_OP
DC
TCK clock pulse width
t_PW
50
TMS, TDI data set-up time
t_DS
5
TMS, TDI data hold time
t_DH
5
TCK low to TDO data valid
t_DV
—
TCK low to TDO tri-state
t_TS
—
TRST assertion time
t_TRST
2T²
1. TCK frequency of operation must be less than 1/8 the processor rate.
2. T = processor clock period (nominally 1/60MHz)
SYS_CLK/8
SYS_CLK/4
—
—
—
30
30
—
Unit
MHz
MHz
ns
ns
ns
ns
ns
ns
See Figure
10-19
10-19
10-19
10-20
10-20
10-20
10-20
10-21
56F8367 Technical Data, Rev. 7.0
Freescale Semiconductor
159
Preliminary