MC56F8367 Datasheet, PDF (149/184 Pages) Freescale Semiconductor, Inc – 16-bit Digital Signal Controllers

External Memory Interface Timing
DCAOE and DCAEO are calculated as follows:
DCAOE = 0.5 - MAX XTAL duty cycle, if ZSRC selects prescaler clock and the prescaler is set to ÷ 1
= 0.0 all other cases
DCAEO = MIN XTAL duty cycle - 0.5, if ZSRC selects prescaler clock and the prescaler is set to ÷ 1
= 0.0 all other cases
Example of DCAOE and DCAEO calculation:
Assuming prescaler is set for ÷ 1 and prescaler clock is selected by ZSRC, if XTAL duty cycle
ranges between 45% and 60% high;
DCAOE = .50 - .60 = - 0.1
DCAEO = .45 - .50 = - 0.05
The timing of write cycles is different when WWS = 0 than when WWS > 0. Therefore, some parameters
contain two sets of numbers to account for this difference. Use the “Wait States Configuration” column
of Table 10-16 to make the appropriate selection.
A0-Axx,CS
RD
WR
t_AWR
t_WRWR
t_WR
t_ARDA
t_RD
t_ARDD
t_WAC
t_WRRD
t_RDA
t_RDRD
t_RDWR
D0-D15
t_DWR
t_DOS
Data Out
t_DOH
t_RDD
t_AD
t_DRD
Data In
Note: During read-modify-write instructions and internal instructions, the address lines do not change state.
Figure 10-4 External Memory Interface Timing
Note:
When multiple lines are given for the same wait state configuration, calculate each and then select the
smallest or most negative.
56F8367 Technical Data, Rev. 7.0
Freescale Semiconductor
149
Preliminary