MC56F8367 Datasheet, PDF (5/184 Pages) Freescale Semiconductor, Inc – 16-bit Digital Signal Controllers

56F8367/56F8167 Features
Part 1 Overview
1.1 56F8367/56F8167 Features
1.1.1 Core
• Efficient 16-bit 56800E family controller engine with dual Harvard architecture
• Up to 60 Million Instructions Per Second (MIPS) at 60MHz core frequency
• Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)
• Four 36-bit accumulators, including extension bits
• Arithmetic and logic multi-bit shifter
• Parallel instruction set with unique DSP addressing modes
• Hardware DO and REP loops
• Three internal address buses and one external address bus
• Four internal data buses and one external data bus
• Instruction set supports both DSP and controller functions
• Controller-style addressing modes and instructions for compact code
• Efficient C compiler and local variable support
• Software subroutine and interrupt stack with depth limited only by memory
• JTAG/EOnCE debug programming interface
1.1.2 Differences Between Devices
Table 1-1 outlines the key differences between the 56F8367 and 56F8167 devices.
Table 1-1 Device Differences
Feature
56F8367
Guaranteed Speed
Program RAM
Data Flash
PWM
CAN
Quad Timer
Quadrature Decoder
Temperature Sensor
Dedicated GPIO
60MHz/60 MIPS
4KB
32KB
2x6
2
4
2x4
1
—
56F8167
40MHZ/40MIPS
Not Available
Not Available
1x6
Not Available
2
1x4
Not Available
7
56F8367 Technical Data, Rev. 7.0
Freescale Semiconductor
5
Preliminary