K30P81M100SF2_11 Datasheet, PDF (50/62 Pages) Freescale Semiconductor, Inc – Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz

Peripheral operating requirements and behaviors
Table 38. SDHC switching specifications
(continued)
Num
Symbol Description
Min.
Max.
Unit
SD5
t_THL
Clock fall time
—
3
ns
SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SD6
t_OD
SDHC output delay (output valid)
-5
6.5
ns
SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SD7
t_THL
SDHC input setup time
5
—
ns
SD8
t_THL
SDHC input hold time
0
—
ns
SDHC_CLK
Output SDHC_CMD
Output SDHC_DAT[3:0]
Input SDHC_CMD
Input SDHC_DAT[3:0]
SD3
SD2
SD6
SD7
SD1
SD8
Figure 23. SDHC timing
6.8.7 _I²_{S switching specifications}
This section provides the AC timings for the I²S in master (clocks driven) and slave
modes (clocks input). All timings are given for non-inverted serial clock polarity
(TCR[TSCKP] = 0, RCR[RSCKP] = 0) and a non-inverted frame sync (TCR[TFSI] = 0,
RCR[RFSI] = 0). If the polarity of the clock and/or the frame sync have been inverted, all
the timings remain valid by inverting the clock signal (I2S_BCLK) and/or the frame sync
(I2S_FS) shown in the figures below.
Table 39. _I²_{S master mode timing}
Num
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
S1
I2S_MCLK cycle time
2 x t_SYS
ns
Table continues on the next page...
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
50
Preliminary
Freescale Semiconductor, Inc.