56F8356 Datasheet, PDF (44/176 Pages) Motorola, Inc – 56F8356 16-bit Hybrid Controller

organized with higher-priority vectors at the top and lower-priority interrupts lower in the table. The
priority of an interrupt can be assigned to different levels, as indicated, allowing some control over
interrupt priorities. All level 3 interrupts will be serviced before level 2, and so on. For a selected priority
level, the lowest vector number has the highest priority.
The location of the vector table is determined by the Vector Base Address (VBA) register. Please see Part
5.6.12 for the reset value of the VBA.
In some configurations, the reset address and COP reset address will correspond to vector 0 and 1 of the
interrupt vector table. In these instances, the first two locations in the vector table must contain branch or
JMP instructions. All other entries must contain JSR instructions.
Note: PWMA, FlexCAN, Quadrature Decoder 1, and Quad Timers B and D are NOT available on the
56F8156 device.
Peripheral
Vector
Number
core
2
core
3
core
4
core
5
core
6
core
7
core
9
core
10
core
11
core
14
core
15
core
16
core
17
core
18
LVI
20
Table 4-5 Interrupt Vector Table Contents¹
Priority Vector Base
Level
Address +
Interrupt Function
Reserved for Reset Overlay²
Reserved for COP Reset Overlay²
3
P:$04
Illegal Instruction
3
P:$06
SW Interrupt 3
3
P:$08
HW Stack Overflow
3
P:$0A
Misaligned Long Word Access
1-3
P:$0C OnCE Step Counter
1-3
P:$0E
OnCE Breakpoint Unit 0
Reserved
1-3
P:$12
OnCE Trace Buffer
1-3
P:$14
OnCE Transmit Register Empty
1-3
P:$16
OnCE Receive Register Full
Reserved
2
P:$1C SW Interrupt 2
1
P:$1E
SW Interrupt 1
0
P:$20
SW Interrupt 0
0-2
P:$22
IRQA
0-2
P:$24
IRQB
Reserved
0-2
P:$28
Low-Voltage Detector (power sense)
56F8356 Technical Data, Rev. 13
44
Freescale Semiconductor
Preliminary