56F8346 Datasheet, PDF (40/176 Pages) Freescale Semiconductor, Inc – 16-bit Digital Signal Controllers

Part 3 On-Chip Clock Synthesis (OCCS)
3.1 Introduction
Refer to the OCCS chapter of the 56F8300 Peripheral User Manual for a full description of the OCCS.
The material contained here identifies the specific features of the OCCS design. Figure 3-1 shows the
specific OCCS block diagram to reference in the OCCS chapter in the 56F8300 Peripheral User Manual.
CLKMODE
XTAL
EXTAL
Crystal
OSC
PLLCID
PLLDB
ZSRC
Prescaler CLK
PLLCOD
SYS_CLK2
Source to SIM
Prescaler
÷ (1,2,4,8)
÷ ^PLL
F_OUT
x (1 to 128)
2
F_{OUT/2 Postscaler}
÷ (1,2,4,8)
Postscaler CLK
Bus Interface & Control
Bus
Interface
Lock
Detector
Loss of
Reference
Clock
Detector
LCK
Loss of Reference
Clock Interrupt
Figure 3-1 OCCS Block Diagram
3.2 External Clock Operation
The system clock can be derived from an external crystal, ceramic resonator, or an external system clock
signal. To generate a reference frequency using the internal oscillator, a reference crystal or ceramic
resonator, must be connected between the EXTAL and XTAL pins.
3.2.1 Crystal Oscillator
The internal oscillator is designed to interface with a parallel-resonant crystal resonator in the frequency
range specified for the external crystal in Table 10-15. A recommended crystal oscillator circuit is shown
in Figure 3-2. Follow the crystal supplier’s recommendations when selecting a crystal, since crystal
parameters determine the component values required to provide maximum stability and reliable start-up.
56F8346 Technical Data, Rev. 15
40
Freescale Semiconductor
Preliminary