56F8346 Datasheet, PDF (13/176 Pages) Freescale Semiconductor, Inc – 16-bit Digital Signal Controllers

Architecture Block Diagram
5
JTAG / EOnCE
CHIP
TAP
Controller
pdb_m[15:0]
pab[20:0]
cdbw[13:0]
56800E
Boot
Flash
Program
Flash
Program
RAM
EMI
17
Address
16
Data
6
Control
Note:
Note:
TAP
Linking
Module
xab1[23:0]
xab2[23:0]
Data
RAM
External
JTAG
Port
cdbr_m[31:0]
xdb2_m[15:0]
Data
Flash
IPBus
Bridge
To Flash
Control Logic
NOT available on the 56F8146 device.
IPBus
Figure 1-1 System Bus Interfaces
Flash
Interface
Units
Flash memories are encapsulated within the Flash Interface Unit (FIU). Flash control is accomplished
by the I/O to the FIU over the peripheral bus, while reads and writes are completed between the core
and the Flash memories.
The primary data RAM port is 32 bits wide. Other data ports are 16 bits.
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
13
Preliminary