56F8346 Datasheet, PDF (27/176 Pages) Freescale Semiconductor, Inc – 16-bit Digital Signal Controllers

Signal Pins
Table 2-2 Signal and Package Information for the 144 Pin LQFP
Signal Name Pin No. Type
State
During
Reset
Signal Description
DS
(CS1)
47
Output
In reset, Data Memory Select — This signal is actually CS1 in the EMI,
output is which is programmed at reset for compatibility with the 56F80x DS
disabled, signal. DS is asserted low for external data memory access.
pull-up is
enabled Depending upon the state of the DRV bit in the EMI bus control
register (BCR), DS is tri-stated when the external bus is inactive.
CS1 resets to provide the DS function as defined on the 56F80x
devices.
(GPIOD9)
Input/
Output
Port D GPIO — This GPIO pin can be individually programmed as
an input or output pin.
GPIOD0
(CS2)
GPIOD1
(CS3)
TXD0
(GPIOE0)
To deactivate the internal pull-up resistor, clear bit 9 in the
GPIOD_PUR register.
48
Input/
Input,
Port D GPIO — These two GPIO pins can be individually
Output
pull-up programmed as input or output pins.
enabled
Output
Chip Select — CS2 - CS3 may be programmed within the EMI
module to act as chip selects for specific areas of the external
49
memory map.
Depending upon the state of the DRV bit in the EMI bus control
register (BCR), CS2 - CS3 are tri-stated when the external bus is
inactive.
Most designs will want to change the DRV state to DRV = 1 instead of
using the default setting.
At reset, these pins are configured as GPIO.
To deactivate the internal pull-up resistor, clear the appropriate
GPIO bit in the GPIOD_PUR register.
Example: GPIOD0, clear bit 0 in the GPIOD_PUR register.
4
Output
In reset, Transmit Data — SCI0 transmit data output
output is
Input/
disabled, Port E GPIO — This GPIO pin can be individually programmed as
Output
pull-up is an input or output pin.
enabled
After reset, the default state is SCI output.
To deactivate the internal pull-up resistor, clear bit 0 in the
GPIOE_PUR register.
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
27
Preliminary