56F8346 Datasheet, PDF (152/176 Pages) Freescale Semiconductor, Inc – 16-bit Digital Signal Controllers

IRQA,
IRQB
A0–A15
t_IRI
Figure 10-8 Interrupt from Wait State Timing
First Interrupt Vector
Instruction Fetch
t_IW
IRQA
A0–A15
t_IF
First Instruction Fetch
Not IRQA Interrupt Vector
Figure 10-9 Recovery from Stop State Using Asynchronous Interrupt Timing
10.10 Serial Peripheral Interface (SPI) Timing
Characteristic
Cycle time
Master
Slave
Enable lead time
Master
Slave
Enable lag time
Master
Slave
Clock (SCK) high time
Master
Slave
Clock (SCK) low time
Master
Slave
Table 10-18 SPI Timing¹
Symbol Min
Max
t_C
50
—
50
—
t_ELD
—
—
25
—
t_ELG
—
—
100
—
t_CH
17.6
—
25
—
t_CL
24.1
—
25
—
Unit
See Figure
10-10, 10-11,
ns
10-12, 10-13
ns
10-13
ns
ns
10-13
ns
ns
10-10, 10-11,
ns
10-12, 10-13
ns
10-13
ns
ns
56F8346 Technical Data, Rev. 15
152
Freescale Semiconductor
Preliminary