MCF5307AI90B Datasheet, PDF (372/484 Pages) Freescale Semiconductor, Inc – Integrated Microprocessor

Freescale Semiconductor, Inc.
MCF5307 Bus Signals
• A[31:24]—Pins are configured as address bits by setting corresponding PAR bits;
they represent the most-significant address bus bits. As much as 4 Gbytes of
memory are available when all of these pins are programmed as address signals.
• PP[15:8]—Pins are configured as parallel port signals by clearing corresponding
PAR bits; these represent the most-significant parallel port bits.
17.2.2 Data Bus (D[31:0])
The data bus is bidirectional and non-multiplexed. Data is sampled by the MCF5307 on the
rising BCLKO edge. The data bus port width, wait states, and internal termination are
initially defined for the boot chip select by D[7:0] during reset. The port width for each chip
select and DRAM bank are programmable. The data bus uses a default configuration if none
of the chip selects or DRAM bank match the address decode. The default configuration is
a 32-bit port with external termination and burst-inhibited transfers. The data bus can
transfer byte, word, or longword data widths. All 32 data bus signals are driven during
writes, regardless of port width and operand size.
D[7:0] are used during reset initialization as inputs to configure the functions as described
in Table 17-3. They are defined in Section 17.5.5, “Data/Configuration Pins (D[7:0]).”
Table 17-3. Data Pin Configuration
Pin
Function
Section
D7 Auto-acknowledge configuration
(AA_CONFIG)
Section 17.5.5.2, “D7—Auto Acknowledge Configuration
(AA_CONFIG)”
D[6:5] Port size configuration (PS_CONFIG[1:0]) Section 17.5.5.3, “D[6:5]—Port Size Configuration
(PS_CONFIG[1:0])”
D4 Address configuration (ADDR_CONFIG/D4) Section 17.5.6, “D4—Address Configuration
(ADDR_CONFIG)”
D[3:2] Frequency Control PLL (FREQ[1:0])
Section 17.5.7, “D[3:2]—Frequency Control PLL (FREQ[1:0] )
D[1:0] Divide Control (DIVIDE[1:0])
Section 17.5.8, “D[1:0]—Divide Control PCLK to BCLKO
(DIVIDE[1:0])
17.2.3 Read/Write (R/W)
When the MCF5307 is the bus master, it drives the R/W signal to indicate the direction of
subsequent data transfers. It is driven high during read bus cycles and driven low during
write bus cycles. This signal is an input during an external master access.
17.2.4 Size (SIZ[1:0])
When it is the bus master, the MCF5307 outputs these signals to indicate the requested data
transfer size. Table 17-4 shows the definition of the bus request size encodings. When the
MCF5307 device is not the bus master, these signals function as inputs.
Note that for misaligned transfers, SIZ[1:0] indicate the size of each transfer. For example,
if a longword access occurs at a misaligned offset of 0x1, a byte is transferred first (SIZ[1:0]
17-8
MCF5307 User’s Manual
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