MCF5307AI90B Datasheet, PDF (295/484 Pages) Freescale Semiconductor, Inc – Integrated Microprocessor

Freescale Semiconductor, Inc.
DMA Controller Module Functional Description
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CLKIN
DREQ0
TM0
TS
A[31:0], SIZ[1:0]
TIP
R/W
TM2
TT0
TT1
CSx, AS
OE, BE/BWE
TA
D[31:0]
Figure 12-13. Single-Address DMA Transfer
12.5.4.2 Auto-Alignment
Auto-alignment allows block transfers to occur at the optimal size based on the address,
byte count, and programmed size. To use this feature, DCR[AA] must be set. The source is
auto-aligned if SSIZE indicates a transfer size larger than DSIZE. Source alignment takes
precedence over the destination when the source and destination sizes are equal. Otherwise,
the destination is auto-aligned. The address register chosen for alignment increments
regardless of the increment value. Configuration error checking is performed on registers
not chosen for alignment.
If BCR is greater than 16, the address determines transfer size. Bytes, words, or longwords
are transferred until the address is aligned to the programmed size boundary, at which time
accesses begin using the programmed size.
If BCR is less than 16 at the start of a transfer, the number of bytes remaining dictates
transfer size. For example, AA = 1, SAR = 0x0001, BCR = 0x00F0, SSIZE = 00
(longword), and DSIZE = 01 (byte). Because SSIZE > DSIZE, the source is auto-aligned.
Error checking is performed on destination registers. The access sequence is as follows:
1. Read byte from 0x0001—write 1 byte, increment SAR.
2. Read word from 0x0002—write 2 bytes, increment SAR.
3. Read longword from 0x0004—write 4 bytes, increment SAR.
Chapter 12. DMA Controller Module
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