MCF5307AI90B Datasheet, PDF (327/484 Pages) Freescale Semiconductor, Inc – Integrated Microprocessor

Freescale Semiconductor, Inc.
UART Module Signal Definitions
The interrupt level, priority, and auto-vectoring capability is programmed in SIM register
ICR4 for UART0 and ICR5 for UART1. See Section 9.2.1, “Interrupt Control Registers
(ICR0–ICR9).”
Note that the UARTs can also automatically transfer data by using the DMA rather than
interrupting the core. When UIMR[FFULL] is 1 and a receiver’s FIFO is full, it can send
an interrupt to a DMA channel so the FIFO data can be transferred to memory. Note also
that UART0 and UART1’s interrupt requests are connected to DMA channel 2 and
channel 3, respectively.
Table 14-13 briefly describes the UART module signals.
NOTE:
The terms ‘assertion’ and ‘negation’ are used to avoid
confusion between active-low and active-high signals.
‘Asserted’ indicates that a signal is active, independent of the
voltage level; ‘negated’ indicates that a signal is inactive.
Table 14-13. UART Module Signals
Signal
Description
Transmitter TxD is held high (mark condition) when the transmitter is disabled, idle, or operating in the local
Serial Data loop-back mode. Data is shifted out on TxD on the falling edge of the clock source, with the least
Output (TxD) significant bit (lsb) sent first.
Receiver
Serial Data
Input (RxD)
Data received on RxD is sampled on the rising edge of the clock source, with the lsb received first.
Clear-to-
This input can generate an interrupt on a change of state.
Send (CTS)
Request-to- This output can be programmed to be negated or asserted automatically by either the receiver or the
Send (RTS) transmitter. When connected to a transmitter’s CTS, RTS can control serial data flow.
Figure 14-18 shows a signal configuration for a UART/RS-232 interface.
UART
RTS
CTS
TxD
RxD
RS-232 Transceiver
DI2
DO2
DI1
DO1
Figure 14-18. UART/RS-232 Interface
Chapter 14. UART Modules
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