MCF5307AI90B Datasheet, PDF (206/484 Pages) Freescale Semiconductor, Inc – Integrated Microprocessor

I²C Protocol
Freescale Semiconductor, Inc.
The slave whose address matches that sent by the master pulls SDA low at the ninth
clock (D) to return an acknowledge bit.
3. Data transfer—When successful slave addressing is achieved, the data transfer can
proceed (E) on a byte-by-byte basis in the direction specified by the R/W bit sent by
the calling master.
Data can be changed only while SCL is low and must be held stable while SCL is
high, as Figure 8-2 shows. SCL is pulsed once for each data bit, with the msb being
sent first. The receiving device must acknowledge each byte by pulling SDA low at
the ninth clock; therefore, a data byte transfer takes nine clock pulses.
If it does not acknowledge the master, the slave receiver must leave SDA high. The
master can then generate a STOP signal to abort the data transfer or generate a
START signal (repeated start, shown in Figure 8-3) to start a new calling sequence.
If the master receiver does not acknowledge the slave transmitter after a byte
transmission, it means end-of-data to the slave. The slave releases SDA for the
master to generate a STOP or START signal.
4. STOP signal—The master can terminate communication by generating a STOP
signal to free the bus. A STOP signal is defined as a low-to-high transition of SDA
while SCL is at logical high (F). Note that a master can generate a STOP even if the
slave has made an acknowledgment, at which point the slave must release the bus.
Instead of signalling a STOP, the master can repeat the START signal, followed by a calling
command, (A in Figure 8-3). A repeated START occurs when a START signal is generated
without first generating a STOP signal to end the communication.
msb
lsb
SCL
1 2 34 5 67 89
msb
lsb
1 234 5 678 9
SDA _{AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W}
XX
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
START
Signal
Calling Address
R/W ACK Repeated
Bit START
Signal _A
New Calling Address
Stop
Figure 8-3. Repeated START
R/W No STOP
ACK Signal
Bit
The master uses a repeated START to communicate with another slave or with the same
slave in a different mode (transmit/receive mode) without releasing the bus.
8.4.1 Arbitration Procedure
If multiple devices simultaneously request the bus, the bus clock is determined by a
synchronization procedure in which the low period equals the longest clock-low period
among the devices and the high period equals the shortest. A data arbitration procedure
8-4
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