M68HC08 Datasheet, PDF (37/188 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Memory
FLASH 2TS Memory
2.5.8.2 PRGRNGE Routine
Name: PRGRNGE
Purpose: Programs a range of addresses in FLASH memory
Entry conditions:
H:X
LADDR
DATA
CPUSPD
BUMPS
Contains the first address in the range
Contains the last address in the range
Contains the data to be programmed (length is user determined)
Contains the bus frequency times 4 in MHz
Contains the maximum allowable number of programming bumps to
use
Exit conditions:
C bit
I bit
Set if successful program; cleared otherwise
Set, masking interrupts
This routine programs a range of FLASH defined by H:X and LADDR. The range
can be from one byte to as much RAM as can be allocated to DATA. The smart
programming algorithm defined in 2.5.4 FLASH 2TS Program/Margin Read
Operation is used.
2.5.8.3 ERARNGE Routine
Name: ERARNGE
Purpose: Erase a range of addresses in FLASH memory
Entry conditions:
H:X
CTLBYTE
DERASE
CPUSPD
Contains an address in the range to be erased; range size specified
by control byte
Contains the erase block size in bits 5 and 6 (see Table 2-6)
Contains the erase delay time in µs/24
CPU frequency times 4 in MHz
Bit 6
0
0
1
1
Table 2-6. CTLBYTE-Erase Block Size
Bit 5
0
1
0
1
Block Size
Full array
One half array
Eight rows: 64 pages
Single row: 8 pages
Exit conditions: I bit
Set, masking interrupts.
MC68HC908RF2 — Rev. 4.0
MOTOROLA
Memory
For More Information On This Product,
Go to: www.freescale.com
Data Sheet
37