M68HC08 Datasheet, PDF (163/188 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
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Monitor Module
While simple monitor commands can access any memory address, the
MC68HC908RF2 has a FLASH security feature to prevent external viewing of the
contents of FLASH. Proper procedures must be followed to verify FLASH content.
Access to the FLASH is denied to unauthorized users of customer-specified
software (see 13.3.2 Security).
In monitor mode, the MCU can execute host-computer code in RAM while all MCU
pins except PTA0 retain normal operating mode functions. All communication
between the host computer and the MCU is through the PTA0 pin. A level-shifting
and multiplexing interface is required between PTA0 and the host computer. PTA0
is used in a wired-OR configuration and requires a pullup resistor.
13.3.1.1 Monitor Mode Entry
Table 13-1 shows the pin conditions for entering monitor mode.
Table 13-1. Monitor Mode Entry
IRQ
PTB0
PTB2
PTA0
Pin
Pin
Pin
Pin
CGMOUNT⁽¹⁾
Bus
Frequency
V_TST(2)
1
0
1
C-----G----M-----X-----C----L---K---
2
C-----G----M------O----U----T---
2
1. If the high voltage (V_TST) is removed from the IRQ pin while in monitor mode, the clock
select bit (CS) controls the source of CGMOUT.
2. For V_TST, see see 14.6 3.0-Volt DC Electrical Characteristics Excluding UHF Module and
14.2 Absolute Maximum Ratings.
NOTE:
Enter monitor mode by either:
• Executing a software interrupt instruction (SWI), or
• Applying a logic 0 and then a logic 1 to the RST pin
Upon entering monitor mode, an interrupt stack frame plus a stacked H register will
leave the stack pointer at address $00F9.
Once out of reset, the MCU waits for the host to send eight security bytes (see
13.3.2 Security). After the security bytes, the MCU sends a break signal (10
consecutive logic 0s) to the host computer, indicating that it is ready to receive a
command.
Monitor mode uses alternate vectors for reset, SWI, and break interrupt. The
alternate vectors are in the $FE page instead of the $FF page and allow code
execution from the internal monitor firmware instead of user code. The COP
module is disabled in monitor mode as long as V_HI (see Section 14. Electrical
Specifications) is applied to either the IRQ1 pin or the RST pin. (See Section 10.
System Integration Module (SIM) for more information on modes of operation.)
The ICG module is bypassed in monitor mode as long as V_HI is applied to the IRQ1
pin. RST does not affect the ICG.
MC68HC908RF2 — Rev. 4.0
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Data Sheet
163