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MC9S08DZ60MLH Datasheet, PDF (341/416 Pages) Freescale Semiconductor, Inc – Microcontrollers | |||
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Chapter 16 Timer/PWM Module (S08TPMV3)
All TPM interrupts are listed in Table 16-8 which shows the interrupt name, the name of any local enable
that can block the interrupt request from leaving the TPM and getting recognized by the separate interrupt
processing logic.
Interrupt
TOF
CHnF
Local
Enable
TOIE
CHnIE
Table 16-8. Interrupt Summary
Source
Description
Counter overï¬ow Set each time the timer counter reaches its terminal
count (at transition to next count value which is
usually 0x0000)
Channel event An input capture or output compare event took
place on channel n
The TPM module will provide a high-true interrupt signal. Vectors and priorities are determined at chip
integration time in the interrupt module so refer to the userâs guide for the interrupt module or to the chipâs
complete documentation for details.
16.6.2 Description of Interrupt Operation
For each interrupt source in the TPM, a ï¬ag bit is set upon recognition of the interrupt condition such as
timer overï¬ow, channel-input capture, or output-compare events. This ï¬ag may be read (polled) by
software to determine that the action has occurred, or an associated enable bit (TOIE or CHnIE) can be set
to enable hardware interrupt generation. While the interrupt enable bit is set, a static interrupt will generate
whenever the associated interrupt ï¬ag equals one. The userâs software must perform a sequence of steps
to clear the interrupt ï¬ag before returning from the interrupt-service routine.
TPM interrupt ï¬ags are cleared by a two-step process including a read of the ï¬ag bit while it is set (1)
followed by a write of zero (0) to the bit. If a new event is detected between these two steps, the sequence
is reset and the interrupt ï¬ag remains set after the second step to avoid the possibility of missing the new
event.
16.6.2.1 Timer Overï¬ow Interrupt (TOF) Description
The meaning and details of operation for TOF interrupts varies slightly depending upon the mode of
operation of the TPM system (general purpose timing functions versus center-aligned PWM operation).
The ï¬ag is cleared by the two step sequence described above.
16.6.2.1.1 Normal Case
Normally TOF is set when the timer counter changes from 0xFFFF to 0x0000. When the TPM is not
conï¬gured for center-aligned PWM (CPWMS=0), TOF gets set when the timer counter changes from the
terminal count (the value in the modulo register) to 0x0000. This case corresponds to the normal meaning
of counter overï¬ow.
MC9S08DZ60 Series Data Sheet, Rev. 4
Freescale Semiconductor
341
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