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MC9S08DZ60MLH Datasheet, PDF (145/416 Pages) Freescale Semiconductor, Inc – Microcontrollers | |||
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Field
5
CME
3:0
VDIV
Chapter 8 Multi-Purpose Clock Generator (S08MCGV1)
Table 8-5. MCG PLL Register Field Descriptions (continued)
Description
Clock Monitor Enable â Determines if a reset request is made following a loss of external clock indication. The
CME bit should only be set to a logic 1 when either the MCG is in an operational mode that uses the external
clock (FEE, FBE, PEE, PBE, or BLPE) or the external reference is enabled (ERCLKEN=1 in the MCGC2
register). Whenever the CME bit is set to a logic 1, the value of the RANGE bit in the MCGC2 register should not
be changed.
0 Clock monitor is disabled.
1 Generate a reset request on loss of external clock.
VCO Divider â Selects the amount to divide down the VCO output of PLL. The VDIV bits establish the
multiplication factor (M) applied to the reference clock frequency.
0000 Encoding 0 â Reserved.
0001 Encoding 1 â Multiply by 4.
0010 Encoding 2 â Multiply by 8.
0011 Encoding 3 â Multiply by 12.
0100 Encoding 4 â Multiply by 16.
0101 Encoding 5 â Multiply by 20.
0110 Encoding 6 â Multiply by 24.
0111 Encoding 7 â Multiply by 28.
1000 Encoding 8 â Multiply by 32.
1001 Encoding 9 â Multiply by 36.
1010 Encoding 10 â Multiply by 40.
1011 Encoding 11 â Reserved (default to M=40).
11xx Encoding 12-15 â Reserved (default to M=40).
MC9S08DZ60 Series Data Sheet, Rev. 4
Freescale Semiconductor
145
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