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MC9S08DZ60MLH Datasheet, PDF (240/416 Pages) Freescale Semiconductor, Inc – Microcontrollers | |||
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Chapter 12 Freescaleâs Controller Area Network (S08MSCANV1)
Field
7:0
AC[7:0]
Table 12-20. CANIDAR0âCANIDAR3 Register Field Descriptions
Description
Acceptance Code Bits â AC[7:0] comprise a user-deï¬ned sequence of bits with which the corresponding bits
of the related identiï¬er register (IDRn) of the receive message buffer are compared. The result of this comparison
is then masked with the corresponding identiï¬er mask register.
7
R
AC7
W
6
AC6
5
AC5
4
AC4
3
AC3
2
AC2
1
AC1
0
AC0
Reset
0
0
0
0
0
0
0
0
Figure 12-20. MSCAN Identiï¬er Acceptance Registers (Second Bank) â CANIDAR4âCANIDAR7
Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
Field
7:0
AC[7:0]
Table 12-21. CANIDAR4âCANIDAR7 Register Field Descriptions
Description
Acceptance Code Bits â AC[7:0] comprise a user-deï¬ned sequence of bits with which the corresponding bits
of the related identiï¬er register (IDRn) of the receive message buffer are compared. The result of this comparison
is then masked with the corresponding identiï¬er mask register.
12.3.16 MSCAN Identiï¬er Mask Registers (CANIDMR0âCANIDMR7)
The identiï¬er mask register speciï¬es which of the corresponding bits in the identiï¬er acceptance register
are relevant for acceptance ï¬ltering. To receive standard identiï¬ers in 32 bit ï¬lter mode, it is required to
program the last three bits (AM[2:0]) in the mask registers CANIDMR1 and CANIDMR5 to âdonât care.â
To receive standard identiï¬ers in 16 bit ï¬lter mode, it is required to program the last three bits (AM[2:0])
in the mask registers CANIDMR1, CANIDMR3, CANIDMR5, and CANIDMR7 to âdonât care.â
R
W
Reset
7
AM7
0
6
AM6
0
5
AM5
0
4
AM4
0
3
AM3
0
2
AM2
0
1
AM1
0
0
AM0
0
Figure 12-21. MSCAN Identiï¬er Mask Registers (First Bank) â CANIDMR0âCANIDMR3
Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
MC9S08DZ60 Series Data Sheet, Rev. 4
240
Freescale Semiconductor
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