MCF53017 Datasheet, PDF (34/62 Pages) Freescale Semiconductor, Inc – Version 3 ColdFire® core with EMAC

Preliminary Electrical Characteristics
5.10 USB On-The-Go
The MCF53017 device is compliant with industry standard USB 2.0 specification.
5.11 SSI Timing Specifications
This section provides the AC timings for the SSI in master (clocks driven) and slave modes (clocks input). All timings are given
for non-inverted serial clock polarity (SSI_TCR[TSCKP] = 0, SSI_RCR[RSCKP] = 0) and a non-inverted frame sync
(SSI_TCR[TFSI] = 0, SSI_RCR[RFSI] = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timings
remain valid by inverting the clock signal (SSI_BCLK) and/or the frame sync (SSI_FS) shown in the figures below.
Table 17. SSI Timing - Master Modes¹
Num
Description
Symbol Min Max
Units Notes
S1 SSI_MCLK cycle time
S2 SSI_MCLK pulse width high / low
S3 SSI_BCLK cycle time
S4 SSI_BCLK pulse width
S5 SSI_BCLK to SSI_FS output valid
t_MCLK 8 × t_SYS —
ns
2
45% 55%
t_MCLK
t_BCLK 8 × t_SYS —
ns
3
45% 55%
t_BCLK
—
15
ns
S6 SSI_BCLK to SSI_FS output invalid
0
—
ns
S7 SSI_BCLK to SSI_TXD valid
—
15
ns
S8 SSI_BCLK to SSI_TXD invalid / high impedence
–2
—
ns
S9 SSI_RXD / SSI_FS input setup before SSI_BCLK
10
—
ns
S10 SSI_RXD / SSI_FS input hold after SSI_BCLK
0
—
ns
1 _{All timings specified with a capactive load of 25pF.}
2 _{SSI_MCLK can be generated from SSI_CLKIN or a divided version of the internal system clock (SYSCLK).}
3 _{SSI_BCLK can be derived from SSI_CLKIN or a divided version of SYSCLK. If the SYSCLK is used, the minimum}
divider is 6. If the SSI_CLKIN input is used, the programmable dividers must be set to ensure that SSI_BCLK does
not exceed 4 x f_SYS.
Table 18. SSI Timing — Slave Modes¹
Num
Description
S11 SSI_BCLK cycle time
S12 SSI_BCLK pulse width high / low
S13 SSI_FS input setup before SSI_BCLK
S14 SSI_FS input hold after SSI_BCLK
S15 SSI_BCLK to SSI_TXD / SSI_FS output valid
S16 SSI_BCLK to SSI_TXD / SSI_FS output invalid / high
impedence
S17 SSI_RXD setup before SSI_BCLK
S18 SSI_RXD hold after SSI_BCLK
1 _{All timings specified with a capactive load of 25pF.}
Symbol Min Max
t_BCLK
8 × t_SYS —
45% 55%
10
—
2
—
—
15
0
—
10
—
2
—
Units
ns
t_BCLK
ns
ns
ns
ns
Notes
ns
ns
MCF5301x Data Sheet, Rev. 3
34
Preliminary—Subject to Change Without Notice
Freescale Semiconductor