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MCF53017 Datasheet, PDF (33/62 Pages) Freescale Semiconductor, Inc – Version 3 ColdFire® core with EMAC
Preliminary Electrical Characteristics
FB_CLK
GPIO Outputs
G1
G2
G3
G4
GPIO Inputs
Figure 18. GPIO Timing
5.9 Reset and Configuration Override Timing
Table 16. Reset and Configuration Override Timing
Num
Characteristic
Symbol
Min
Max Unit
R1 RESET Input valid to FB_CLK High
tRVCH
9
—
ns
R2 FB_CLK High to RESET Input invalid
R3 RESET Input valid Time 1
tCHRI
1.5
tRIVT
5
—
ns
—
tCYC
R4 FB_CLK High to RSTOUT Valid
tCHROV
—
10
ns
R5 RSTOUT valid to Config. Overrides valid
tROVCV
0
—
ns
R6 Configuration Override Setup Time to RSTOUT invalid
tCOS
20
—
tCYC
R7 Configuration Override Hold Time after RSTOUT invalid
tCOH
0
—
ns
R8 RSTOUT invalid to Configuration Override High Impedance
tROICZ
—
1
tCYC
1 During low power STOP, the synchronizers for the RESET input are bypassed and RESET is asserted asynchronously to
the system. Thus, RESET must be held a minimum of 100 ns.
FB_CLK
R1
RESET
RSTOUT
Configuration Overrides*:
(RCON, Override pins])
R2
R3
R4
R5
R4
R8
R6
R7
Figure 19. RESET and Configuration Override Timing
NOTE
Refer to the CCM chapter of the MCF5301x Reference Manual for more information.
MCF5301x Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
33