MCF53017 Datasheet, PDF (31/62 Pages) Freescale Semiconductor, Inc – Version 3 ColdFire® core with EMAC

Preliminary Electrical Characteristics
8 _{Data input skew is derived from each DQS clock edge. It begins with a DQS transition and ends when the last data line}
becomes valid. This input skew must include DDR memory output skew and system level board skew (due to routing or other
factors).
9 _{Data input hold is derived from each DQS clock edge. It begins with a DQS transition and ends when the first data line becomes}
invalid.
SD_CLK
SD_CLK
Figure 15. SD_CLK and SD_CLK Crossover Timing
V_IX
V_MP ^V_ID
V_IX
SD_CLK
SD_CLK
SD_CSn,SD_WE,
SD_RAS, SD_CAS
A[13:0]
DM3/DM2
SD_DQS3/SD_DQS2
D[31:24]/D[23:16]
DD1
DD2
DD3
DD5
CMD
DD4
DD6
ROW
COL
DD7
DD8
DD7
WD1 WD2 WD3 WD4
DD8
Figure 16. DDR Write Timing
MCF5301x Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
31