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S9S08DZ32F1CLH Datasheet, PDF (328/416 Pages) Freescale Semiconductor, Inc – HC08 instruction set with added BGND instruction | |||
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Chapter 16 Timer/PWM Module (S08TPMV3)
16.3 Register Deï¬nition
This section consists of register descriptions in address order. A typical MCU system may contain multiple
TPMs, and each TPM may have one to eight channels, so register names include placeholder characters to
identify which TPM and which channel is being referenced. For example, TPMxCnSC refers to timer
(TPM) x, channel n. TPM1C2SC would be the status and control register for channel 2 of timer 1.
16.3.1 TPM Status and Control Register (TPMxSC)
TPMxSC contains the overï¬ow status ï¬ag and control bits used to conï¬gure the interrupt enable, TPM
conï¬guration, clock source, and prescale factor. These controls relate to all channels within this timer
module.
7
6
5
4
3
2
1
0
R TOF
TOIE
CPWMS
CLKSB
CLKSA
PS2
PS1
PS0
W
0
Reset
0
0
0
0
0
0
0
0
Figure 16-7. TPM Status and Control Register (TPMxSC)
Table 16-2. TPMxSC Field Descriptions
Field
Description
7
TOF
6
TOIE
5
CPWMS
Timer overï¬ow ï¬ag. This read/write ï¬ag is set when the TPM counter resets to 0x0000 after reaching the modulo
value programmed in the TPM counter modulo registers. Clear TOF by reading the TPM status and control
register when TOF is set and then writing a logic 0 to TOF. If another TPM overï¬ow occurs before the clearing
sequence is complete, the sequence is reset so TOF would remain set after the clear sequence was completed
for the earlier TOF. This is done so a TOF interrupt request cannot be lost during the clearing sequence for a
previous TOF. Reset clears TOF. Writing a logic 1 to TOF has no effect.
0 TPM counter has not reached modulo value or overï¬ow
1 TPM counter has overï¬owed
Timer overï¬ow interrupt enable. This read/write bit enables TPM overï¬ow interrupts. If TOIE is set, an interrupt is
generated when TOF equals one. Reset clears TOIE.
0 TOF interrupts inhibited (use for software polling)
1 TOF interrupts enabled
Center-aligned PWM select. When present, this read/write bit selects CPWM operating mode. By default, the
TPM operates in up-counting mode for input capture, output compare, and edge-aligned PWM functions. Setting
CPWMS reconï¬gures the TPM to operate in up/down counting mode for CPWM functions. Reset clears CPWMS.
0 All channels operate as input capture, output compare, or edge-aligned PWM mode as selected by the
MSnB:MSnA control bits in each channelâs status and control register.
1 All channels operate in center-aligned PWM mode.
MC9S08DZ60 Series Data Sheet, Rev. 4
328
Freescale Semiconductor
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