|
S9S08DZ32F1CLH Datasheet, PDF (202/416 Pages) Freescale Semiconductor, Inc – HC08 instruction set with added BGND instruction | |||
|
◁ |
Chapter 11 Inter-Integrated Circuit (S08IICV2)
11.1.3 Block Diagram
Figure 11-2 is a block diagram of the IIC.
Address
ADDR_DECODE
Interrupt
Data Bus
DATA_MUX
CTRL_REG FREQ_REG ADDR_REG
STATUS_REG
DATA_REG
Input
Sync
Clock
Control
Start
Stop
Arbitration
Control
In/Out
Data
Shift
Register
Address
Compare
SCL
SDA
Figure 11-2. IIC Functional Block Diagram
11.2 External Signal Description
This section describes each user-accessible pin signal.
11.2.1 SCL â Serial Clock Line
The bidirectional SCL is the serial clock line of the IIC system.
11.2.2 SDA â Serial Data Line
The bidirectional SDA is the serial data line of the IIC system.
11.3 Register Deï¬nition
This section consists of the IIC register descriptions in address order.
MC9S08DZ60 Series Data Sheet, Rev. 4
202
Freescale Semiconductor
|
▷ |