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S9S08DZ32F1CLH Datasheet, PDF (254/416 Pages) Freescale Semiconductor, Inc – HC08 instruction set with added BGND instruction | |||
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Chapter 12 Freescaleâs Controller Area Network (S08MSCANV1)
ï¬eld of the CAN frame, is received into the next available RxBG. If the MSCAN receives an invalid
message in its RxBG (wrong identiï¬er, transmission errors, etc.) the actual contents of the buffer will be
over-written by the next message. The buffer will then not be shifted into the FIFO.
When the MSCAN module is transmitting, the MSCAN receives its own transmitted messages into the
background receive buffer, RxBG, but does not shift it into the receiver FIFO, generate a receive interrupt,
or acknowledge its own messages on the CAN bus. The exception to this rule is in loopback mode (see
Section 12.3.2, âMSCAN Control Register 1 (CANCTL1)â) where the MSCAN treats its own messages
exactly like all other incoming messages. The MSCAN receives its own transmitted messages in the event
that it loses arbitration. If arbitration is lost, the MSCAN must be prepared to become a receiver.
An overrun condition occurs when all receive message buffers in the FIFO are ï¬lled with correctly
received messages with accepted identiï¬ers and another message is correctly received from the CAN bus
with an accepted identiï¬er. The latter message is discarded and an error interrupt with overrun indication
is generated if enabled (see Section 12.5.7.5, âError Interruptâ). The MSCAN remains able to transmit
messages while the receiver FIFO is full, but all incoming messages are discarded. As soon as a receive
buffer in the FIFO is available again, new valid messages will be accepted.
12.5.3 Identiï¬er Acceptance Filter
The MSCAN identiï¬er acceptance registers (see Section 12.3.11, âMSCAN Identiï¬er Acceptance Control
Register (CANIDAC)â) deï¬ne the acceptable patterns of the standard or extended identiï¬er (ID[10:0] or
ID[28:0]). Any of these bits can be marked âdonât careâ in the MSCAN identiï¬er mask registers (see
Section 12.3.16, âMSCAN Identiï¬er Mask Registers (CANIDMR0âCANIDMR7)â).
A ï¬lter hit is indicated to the application software by a set receive buffer full ï¬ag (RXF = 1) and three bits
in the CANIDAC register (see Section 12.3.11, âMSCAN Identiï¬er Acceptance Control Register
(CANIDAC)â). These identiï¬er hit ï¬ags (IDHIT[2:0]) clearly identify the ï¬lter section that caused the
acceptance. They simplify the application softwareâs task to identify the cause of the receiver interrupt. If
more than one hit occurs (two or more ï¬lters match), the lower hit has priority.
A very ï¬exible programmable generic identiï¬er acceptance ï¬lter has been introduced to reduce the CPU
interrupt loading. The ï¬lter is programmable to operate in four different modes (see Bosch CAN 2.0A/B
protocol speciï¬cation):
⢠Two identiï¬er acceptance ï¬lters, each to be applied to:
â The full 29 bits of the extended identiï¬er and to the following bits of the CAN 2.0B frame:
â Remote transmission request (RTR)
â Identiï¬er extension (IDE)
â Substitute remote request (SRR)
â The 11 bits of the standard identiï¬er plus the RTR and IDE bits of the CAN 2.0A/B messages1.
This mode implements two ï¬lters for a full length CAN 2.0B compliant extended identiï¬er.
Figure 12-39 shows how the ï¬rst 32-bit ï¬lter bank (CANIDAR0âCANIDAR3,
CANIDMR0âCANIDMR3) produces a ï¬lter 0 hit. Similarly, the second ï¬lter bank
(CANIDAR4âCANIDAR7, CANIDMR4âCANIDMR7) produces a ï¬lter 1 hit.
1.Although this mode can be used for standard identifiers, it is recommended to use the four or eight identifier acceptance
filters for standard identifiers
MC9S08DZ60 Series Data Sheet, Rev. 4
254
Freescale Semiconductor
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