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S9S08DZ32F1CLH Datasheet, PDF (255/416 Pages) Freescale Semiconductor, Inc – HC08 instruction set with added BGND instruction | |||
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Chapter 12 Freescaleâs Controller Area Network (S08MSCANV1)
⢠Four identiï¬er acceptance ï¬lters, each to be applied to
â a) the 14 most signiï¬cant bits of the extended identiï¬er plus the SRR and IDE bits of CAN 2.0B
messages or
â b) the 11 bits of the standard identiï¬er, the RTR and IDE bits of CAN 2.0A/B messages.
Figure 12-40 shows how the ï¬rst 32-bit ï¬lter bank (CANIDAR0âCANIDA3,
CANIDMR0â3CANIDMR) produces ï¬lter 0 and 1 hits. Similarly, the second ï¬lter bank
(CANIDAR4âCANIDAR7, CANIDMR4âCANIDMR7) produces ï¬lter 2 and 3 hits.
⢠Eight identiï¬er acceptance ï¬lters, each to be applied to the ï¬rst 8 bits of the identiï¬er. This mode
implements eight independent ï¬lters for the ï¬rst 8 bits of a CAN 2.0A/B compliant standard
identiï¬er or a CAN 2.0B compliant extended identiï¬er. Figure 12-41 shows how the ï¬rst 32-bit
ï¬lter bank (CANIDAR0âCANIDAR3, CANIDMR0âCANIDMR3) produces ï¬lter 0 to 3 hits.
Similarly, the second ï¬lter bank (CANIDAR4âCANIDAR7, CANIDMR4âCANIDMR7)
produces ï¬lter 4 to 7 hits.
⢠Closed ï¬lter. No CAN message is copied into the foreground buffer RxFG, and the RXF ï¬ag is
never set.
CAN 2.0B
Extended Identiï¬er ID28
IDR0
ID21 ID20
IDR1
ID15 ID14
IDR2
CAN 2.0A/B
Standard Identiï¬er
ID10
IDR0
ID3 ID2
IDR1 IDE
ID10
IDR2
ID7 ID6
IDR3
RTR
ID3 ID10
IDR3
ID3
AM7 CANIDMR0 AM0 AM7 CANIDMR1 AM0 AM7 CANIDMR2 AM0 AM7 CANIDMR3 AM0
AC7
CANIDAR0
AC0 AC7
CANIDAR1
AC0 AC7
CANIDAR2
AC0 AC7
CANIDAR3
AC0
ID Accepted (Filter 0 Hit)
Figure 12-39. 32-bit Maskable Identiï¬er Acceptance Filter
MC9S08DZ60 Series Data Sheet, Rev. 4
Freescale Semiconductor
255
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