MC9S08MM128 Datasheet, PDF (32/50 Pages) Freescale Semiconductor, Inc – Advanced Information

Preliminary Electrical Characteristics
2.10 MCG and External Oscillator (XOSC) Characteristics
Table 17. MCG (Temperature Range = –40 to 105°C Ambient)
#
Rating
Symbol Min Typical Max Unit C
1 Internal reference startup time
factory trimmed at
VDD=3.0 V and
2 Average internal reference frequency _temp=25°C
t_irefst
f_{int_ft}
—
55
100
μs D
—
31.25
C
—
kHz
user trimmed
31.25
—
39.0625
C
3
DCO output frequency range -
trimmed
Low range
(DRS=00)
Mid range
(DRS=01)
High range¹
(DRS=10)
16
—
f_{dco_t}
32
—
40
—
20
C
MHz
40
C
60
C
Resolution of trimmed DCO output fre- with FTRIM
4 quency at fixed voltage and tempera-
ture
without FTRIM
—
Δf_{dco_res_t}
—
± 0.1
± 0.2
± 0.2
± 0.4
C
%f_{dco C}
over voltage and
Total deviation of trimmed DCO output ^temperature
—
5 frequency over voltage and tempera- _{over fixed voltage}
Δf_{dco_t}
ture
and temp range
—
of 0 - 70 °C
6 ^{Acquisition time}
FLL²
PLL³
t_{fll_acquire}
—
t_{pll_acquire}
—
±1.0
± 0.5
—
—
±2
p
%f_{dco C}
±1
1
C
ms
1
D
7
Long term Jitter of DCO output clock (averaged over 2mS
interval) ⁴
C_Jitter
—
0.02
0.2
%f_dco ^C
8 VCO operating frequency
f_vco
7.0
—
55.0 MHz D
9 PLL reference frequency range
f_{pll_ref}
1.0
—
2.0
MHz D
10
Jitter of PLL output clock measured
over 625ns ⁵
11 Lock frequency tolerance
Long term
Entry⁶
Exit⁷
f_{pll_jitter_625}
ns
D_lock
D_unl
—
± 1.49
± 4.47
0.566⁴
—
—
—
± 2.98
± 5.97
%f_pll ^D
D
%
D
12 Lock time
FLL
PLL
t_{fll_lock}
—
t_{pll_lock}
—
—
t_{fll_acquire+}
1075(1/^fint_t)
D
t_{pll_acquire+} ^s
D
—
1075(1/^fpll_re
f)
Loss of external clock minimum frequency - RANGE = 0
13
f_{loc_low}
(3/5) x
f_{int_t}
—
D
—
kHz
Loss of external clock minimum frequency - RANGE = 1
14
f_{loc_high}
(16/5) x
f_{int_t}
—
D
—
kHz
1 _{This should not exceed the maximum CPU frequency for this device.}
2 _{This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,}
DMX32 bit is changed, DRS bit is changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
32
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Preliminary — Subject to Change