MC9S08MM128 Datasheet, PDF (14/50 Pages) Freescale Semiconductor, Inc – Advanced Information

Preliminary Electrical Characteristics
2.2 Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the
limits specified in the following table may affect device reliability or cause permanent damage to the device. For functional
operating conditions, refer to the remaining tables in this section.
Table 5. Absolute Maximum Ratings
#
Rating
Symbol
Value
Unit
1 Supply voltage
2 Maximum current into V_DD
3 Digital input voltage
4
Instantaneous maximum current
Single pin limit (applies to all port pins)^{1, 2, 3}
V_DD
–0.3 to +3.8
V
I_DD
120
mA
V_In
–0.3 to V_DD + 0.3
V
I_D
± 25
mA
5 Storage temperature range
T_stg
–55 to 150
°C
1 _{Input must be current limited to the value specified. To determine the value of the required}
current-limiting resistor, calculate resistance values for positive (V_DD) and negative (V_SS) clamp
voltages, then use the larger of the two resistance values.
2 _{All functional non-supply pins are internally clamped to VSS and VDD.}
3 _{Power supply must maintain regulation within operating VDD range during instantaneous and operating}
maximum current conditions. If positive injection current (V_In > V_DD) is greater than I_DD, the injection
current may flow out of V_DD and could result in external power supply going out of regulation. Ensure
external V_DD load will shunt current greater than maximum injection current. This will be the greatest
risk when the MCU is not consuming power. Examples are: if no system clock is present, or if the clock
rate is very low (which would reduce overall power consumption).
This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised
that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this
high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for
instance, either V_SS or V_DD).
14
Freescale Semiconductor
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Preliminary — Subject to Change