MC9S08MM128 Datasheet, PDF (25/50 Pages) Freescale Semiconductor, Inc – Advanced Information

Preliminary Electrical Characteristics
Table 14. DAC 12-Bit Operating Behaviors
#
Characteristic
Symbol
Min
Max
1 Resolution
N
12
12
2 ^{Supply current low-power mode}
I_{DDA_DACLP 50}
100
3 ^{Supply current high-power mode}
I_{DDA_DACHP 120}
500
(TBD)
Full-scale Settling time
Ts_FSLP
4
(±0.5 LSB)
(0x080 to 0xF7F or 0xF7F to 0x080)
—
low-power mode
200
(TBD)
Full-scale Settling time
Ts_FSHP
5
(±0.5 LSB)
(0x080 to 0xF7F or 0xF7F to 0x080)
—
30
high-power mode
Code-to-code Settling time
(±0.5 LSB)
6 (0xBF8 to 0xC08 or 0xC08 to
0xBF8)
low-power mode
Ts_C-CLP
—
5
Code-to-code Settling time
(±0.5 LSB)
7 (0xBF8 to 0xC08 or 0xC08 to
0xBF8)
high-power mode
Ts_C-CHP
—
1(TBD)
DAC output voltage range low
8 (high-power mode, no load, DAC
set to 0)
V_dacoutl
—
100
(TBD)
DAC output voltage range high
9 (high-power mode, no load, DAC
set to 0x0FFF)
V_dacouth
V_DACR-
100
—
10 Integral non-linearity error
INL
—
±8
11
Differential non-linearity error
VDACR is > 2.4 V
DNL
—
±1
12 Offset error
13 ^{Gain error}
E_O
—
± 0.5
E_G
—
± 0.5
(TBD)
14
Power supply rejection ratio
V_DD ≥ 2.4 V
Temperature drift of offset voltage
15 (DAC set to 0x0800)
PSRR
60
T_co
—
—
2
(TBD)
16 Offset aging coefficient
A_c
—
TBD
Unit C
bit
C
µA
C
µA
C
µs
C
Notes
µs
C
µs
C
µs
C
mV
C
mV
C
LSB
C
LSB
C
%FSR C
%FSR C
dB
C
mV
C
µV/yr C
See Typical
Drift figure that
follows.
Figure 6. Offset at Half Scale vs Temperature
Freescale Semiconductor
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Preliminary — Subject to Change