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MC9S08SH8CTG Datasheet, PDF (316/341 Pages) Freescale Semiconductor, Inc – HCS08 Microcontrollers | |||
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Appendix A Electrical Characteristics
A.12.3 SPI
Table A-15 and Figure A-14 through Figure A-17 describe the timing requirements for the SPI system.
Table A-15. SPI Electrical Characteristic
Num1 C
Rating2
Symbol
Min
Max
Unit
1
D Cycle time
Master tSCK
2
Slave tSCK
4
2048
tcyc
â
tcyc
2
D Enable lead time
Master tLead
â
Slave tLead
1/2
1/2
tSCK
â
tSCK
3
D Enable lag time
Master tLag
â
Slave tLag
1/2
1/2
tSCK
â
tSCK
4
D Clock (SPSCK) high time
Master and Slave tSCKH 1/2 tSCK â 25
â
ns
5
D Clock (SPSCK) low time
Master and Slave tSCKL 1/2 tSCK â 25
â
ns
6
D Data setup time (inputs)
Master tSI(M)
30
Slave tSI(S)
30
â
ns
â
ns
7
D Data hold time (inputs)
Master tHI(M)
30
Slave tHI(S)
30
8
D Access time, slave3
tA
0
9
D Disable time, slave4
tdis
â
â
ns
â
ns
40
ns
40
ns
10
D Data setup time (outputs)
Master tSO
25
Slave tSO
25
â
ns
â
ns
11
D Data hold time (outputs)
Master tHO
â10
Slave tHO
â10
â
ns
â
ns
12
D Operating frequency
Master fop
Slave fop
fBus/2048
dc
55
fBus/4
MHz
1 Refer to Figure A-14 through Figure A-17.
2 All timing is shown with respect to 20% VDD and 70% VDD, unless noted; 100 pF load on all SPI
pins. All timing assumes slew rate control disabled and high drive strength enabled for SPI output
pins.
3 Time to data active from high-impedance state.
4 Hold time to high-impedance state.
5 Maximum baud rate must be limited to 5 MHz due to input ï¬lter characteristics.
MC9S08SH8 MCU Series Data Sheet, Rev. 3
312
Freescale Semiconductor
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