34704_11 Datasheet, PDF (31/54 Pages) Freescale Semiconductor, Inc – Multiple Channel DC-DC Power Management IC

FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
processor decision to either shutoff or not, in the mean time
the control loop will try to fix itself.
To avoid erroneous conditions, a 20 μs filter will be
implemented.
The OV/UV fault flag is masked during DVS until
DVSSTAT flag is asserted “Done”.
To keep the RST output low during ramp up and until the
soft start is done, the OV/UV protection is masked from
reporting that the output is in regulation.
LOGIC COMMANDS AND REGISTERS
I²C USER INTERFACE
The 34704 communicates via I²C using a default device
address $54 to access all user registers and program all
regulators features independently. Physical address is in a 7-
bit format. The extra bit to complete the 8-bit indicates the
reading or writing mode as shown in Figure 7 and Figure 8.
After each byte read or sent, the MC34704 answers with an
Acknowledge bit, indicating the bite was transferred
successfully.
7 bit Physical Address +
(w) bit
1010100 + 0
ACK
0
Sub-Address
(MSB=0)
0XXXXXXX
ACK
Data
ACK
0 XXXXXXXX 0
Start Bit
ACK
ACK
ACK End Bit
10101 000 0000001 0 00001111
Figure 7. Writing sequence I²C bit stream
7 bit Physical ADD + _ACK
(w) bit
Sub-address
(MSB=1)
ACK
RS
1010100 + 0
0 1XXXXXXX
01
Ph ysical
ADD + (r) bit
1010100 + 1
ACK
0
Data Read
XXXXXXX
ACK
1
Start Bit
ACK
ACK
ACK
ACK End Bit
1 0 10 1 00
1 0 0 0 0 0 0 _RS 1 0 1 0 1 0 0
Figure 8. Reading sequence I²C bit stream
0 0 01 1 11 1
USER PROGRAMMABLE REGISTERS
GrpC/E power sequencing setting (34704A Only)
The microprocessor can choose one of several voltage
sequence options for the GrpC/E supply (REG5), high
voltage supply (REG6), and negative voltage supply (REG7).
For 3 of the sequencing options, REG5 supply is controlled
and tied with REG6 and REG7 in a preset power sequence.
By default, only REG6 and REG7 are involved in the power
sequence and REG5 is independently controlled with GrpE.
34704A assigns 2 bits to program the GrpC/E power
sequencing options (CCDSEQ[1:0]). These bits value is
latched in at GrpC power up and will not be allowed to change
unless a power recycle happens.
OPTION
1
(Default)
MSB
0
LSB
0
GRPC/E ENABLED
REG5 is independently controlled
REG6 and REG7 ramp up together.
GRPC/E DISABLED
REG5 is independently controlled
REG6 and REG7 ramp down together
Analog Integrated Circuit Device Data
Freescale Semiconductor
34704
31