MC68HC908QY4A_10 Datasheet, PDF (30/200 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Memory
ERASE — Erase Control Bit
This read/write bit configures the memory for erase operation. ERASE is interlocked with the PGM bit
such that both bits cannot be equal to 1 or set to 1 at the same time.
1 = Erase operation selected
0 = Erase operation unselected
PGM — Program Control Bit
This read/write bit configures the memory for program operation. PGM is interlocked with the ERASE
bit such that both bits cannot be equal to 1 or set to 1 at the same time.
1 = Program operation selected
0 = Program operation unselected
2.6.2 FLASH Page Erase Operation
Use the following procedure to erase a page of FLASH memory. A page consists of 64 consecutive bytes
starting from addresses $XX00, $XX40, $XX80, or $XXC0. The user interrupt vector area resides in the
$FFC0–$FFFF page. Any FLASH memory page can be erased alone.
1. Set the ERASE bit and clear the MASS bit in the FLASH control register.
2. Read the FLASH block protect register.
3. Write any data to any FLASH location within the address range of the block to be erased.
4. Wait for a time, t_NVS.
5. Set the HVEN bit.
6. Wait for a time, t_Erase.
7. Clear the ERASE bit.
8. Wait for a time, t_NVH.
9. Clear the HVEN bit.
10. After time, t_RCV, the memory can be accessed in read mode again.
NOTE
The COP register at location $FFFF should not be written between steps
5-9, when the HVEN bit is set. Since this register is located at a valid
FLASH address, unpredictable behavior may occur if this location is written
while HVEN is set.
NOTE
Programming and erasing of FLASH locations cannot be performed by
code being executed from the FLASH memory. While these operations
must be performed in the order as shown, other unrelated operations may
occur between the steps.
CAUTION
A page erase of the vector page will erase the internal oscillator trim values
at $FFC0 and $FFC1.
MC68HC908QYA/QTA Family Data Sheet, Rev. 3
30
Freescale Semiconductor