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MC9S08DV60 Datasheet, PDF (242/414 Pages) Freescale Semiconductor, Inc – HCS08 Microcontrollers | |||
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Chapter 12 Freescaleâs Controller Area Network (S08MSCANV1)
Section 12.3.10, âMSCAN Transmit Buffer Selection Register (CANTBSEL)â). For receive buffers, only
when RXF ï¬ag is set (see Section 12.3.4.1, âMSCAN Receiver Flag Register (CANRFLG)â).
Write: For transmit buffers, anytime when TXEx ï¬ag is set (see Section 12.3.6, âMSCAN Transmitter Flag
Register (CANTFLG)â) and the corresponding transmit buffer is selected in CANTBSEL (see
Section 12.3.10, âMSCAN Transmit Buffer Selection Register (CANTBSEL)â). Unimplemented for
receive buffers.
Reset: Undeï¬ned (0x00XX) because of RAM-based implementation
Register
Name
Bit 7
6
5
4
3
2
1
Bit 0
R
IDR0
ID10
ID9
ID8
ID7
ID6
ID5
ID4
ID3
W
IDR1
R
ID2
ID1
ID0
RTR1
IDE2
W
R
IDR2
W
R
IDR3
W
= Unused, always read âxâ
Figure 12-24. Receive/Transmit Message Buffer â Standard Identiï¬er Mapping
1 The position of RTR differs between extended and standard indentiï¬er mapping.
2 IDE is 0.
12.4.1 Identiï¬er Registers (IDR0âIDR3)
The identiï¬er registers for an extended format identiï¬er consist of a total of 32 bits; ID[28:0], SRR, IDE,
and RTR bits. The identiï¬er registers for a standard format identiï¬er consist of a total of 13 bits; ID[10:0],
RTR, and IDE bits.
12.4.1.1 IDR0âIDR3 for Extended Identiï¬er Mapping
R
W
Reset:
7
ID28
6
ID27
5
ID26
4
ID25
3
ID24
2
ID23
1
ID22
x
x
x
x
x
x
x
Figure 12-25. Identiï¬er Register 0 (IDR0) â Extended Identiï¬er Mapping
0
ID21
x
MC9S08DV60 Series Data Sheet, Rev 3
242
Freescale Semiconductor
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