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MC9S08DV60 Datasheet, PDF (140/414 Pages) Freescale Semiconductor, Inc – HCS08 Microcontrollers | |||
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Chapter 8 Multi-Purpose Clock Generator (S08MCGV1)
8.3.3 MCG Trim Register (MCGTRM)
7
R
W
POR:
1
Reset:
U
6
5
4
3
TRIM
2
1
0
0
0
0
0
0
0
0
U
U
U
U
U
U
U
Figure 8-5. MCG Trim Register (MCGTRM)
Table 8-3. MCG Trim Register Field Descriptions
Field
7:0
TRIM
Description
MCG Trim Setting â Controls the internal reference clock frequency by controlling the internal reference clock
period. The TRIM bits are binary weighted (i.e., bit 1 will adjust twice as much as bit 0). Increasing the binary
value in TRIM will increase the period, and decreasing the value will decrease the period.
An additional ï¬ne trim bit is available in MCGSC as the FTRIM bit.
If a TRIM[7:0] value stored in nonvolatile memory is to be used, itâs the userâs responsibility to copy that value
from the nonvolatile memory location to this register.
MC9S08DV60 Series Data Sheet, Rev 3
140
Freescale Semiconductor
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