MC68EC030FE40C Datasheet, PDF (24/36 Pages) Freescale Semiconductor, Inc – Second-Generation 32-Bit Enhanced Embedded Controller

Freescale Semiconductor, Inc.
2.0 V
0.8 V
4
1
2
3
5
NOTE: ^{Timing measurements are referenced to and from a low voltage of 0.8 V and a high voltage of 2.0 V, unless otherwise noted.}
The voltage swing through this range should start outside and pass through the range so that the rise or fall will be
linear between 0.8 V and 2.0 V.
Figure 10. Clock Input Timing Diagram
AC ELECTRICAL SPECIFICATIONS -- READ AND WRITE CYCLES
(V_CC=5.0Vdc ± 5%; GND=0 Vdc; temperature in defined ranges; see Figures 11–16)
Num.
Characterstics
25MHz 40 MHz Unit
Min Max Min Max
6
Clock High to Function Code, Size, RMC, IPEND,CIOUT,
Address Valid
0 20 0 14 ns
6A Clock High to ECS, OCS Asserted
0 15 0 10 ns
6B ^{Function Code, Size, RMC, IPEND, CIOUT, Address Valid to}
Negating Edge of ECS
3—
3
—
ns
7
Clock High to Function Code Size, RMC, CIOUT, Address Data
High Impedance
0 40 0 25 ns
8
Clock High to Function Code Size, RMC, IPEND, CIOUT, Address ₀
—
0
—
ns
Invalid
9
9A¹
9B¹⁴
Clock Low to AS, DS Asserted, CBREQ Valid
AS to DS Assertion Skew (Read)
AS Asserted to DS Asserted (Write)
3 18 2 10 ns
-10 10 -6
6
ns
27 — 16 —
ns
10 ECS Width Asserted
10 —
5
—
ns
10A OCS Width Asserted
10B⁷ ECS, OCS Width Negated
10 —
5
—
ns
5—
5
—
ns
11 ^{Function Code, Size, RMC, CIOUT, Address Valid to AS Asserted} 7
—
5
—
ns
(and DS Asserted, Read)
12 Clock Low to AS, DS, CBREQ Negated
0 18 0 10 ns
12A Clock Low to ECS/OCS Negated
0 18 0 12 ns
13 ^{AS, DS Negated to Function Code, Size, RMC CIOUT, Address}
Invalid
7—
3
—
ns
14 AS (and DS Read) Width Asserted (Asynchronous Cycle)
14A¹¹ DS Width Asserted (Write)
70 — 30 —
ns
30 — 18 —
ns
14B AS (and DS, Read) Width Asserted (Synchronous Cycle)
30 — 18 —
ns
15 AS, DS Width Negated
30 — 18 —
ns
24
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